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Page history last edited by vbottoni@... 16 years ago

Cal Poly, San Luis Obispo

 

Winter 2008, EE 307

Instructor: Dr. Braun

http://s01g01ee307w08.pbwiki.com

 

 

CMOS AND Gate Project

Section 1: Group 1

 

Members:

 

Vincent Bottoni (vbottoni@calpoly.edu), Clay Hadick (chadick@calpoly.edu)

Edward Adams (eadams@calpoly.edu), John Burkett (jwburket@calpoly.edu)

 


Appendix

 

 

Welcome to group one's CMOS AND Gate Project page. Here we have a summary of performance specifications for four different AND Gates. Ultimately, we grade each gate on its Figure of Merit (FOM, defined below). This makes a gate with a low FOM the most desirable.

 

Summary Area (µm2)

Delay (ns)

Power Dissipation (mW) FOM***

Big 2 Level AND

34.5

1.4

0.750

38.8
Med 2 Level AND 13.5 1.25 0.720 12.15
4 Level AND 38.5 0.775 1.14 34.01
Custom AND 2.125  3.865   0.346  2.841

 

 

 

 

 

 

 

 

 ***FOM (Figure of Merit) = Area (µm2) x Delay (ns) x Power Dissipation (mW)

 

 

 

 

 

 

 Table 1 - AND gate comparison summary

 

 

Summary of Our Analysis and Design

 

 

Figure 1 - BIG TWO LEVEL AND: An eight-input NAND gate followed by an inverter

 

 

In Figure 1, we have an eight input CMOS NAND gate followed by a simple CMOS inverter. The inverter outputs the desired AND function from the NAND gate. The NAND gate consists of 8 PMOSFETS in parallel and 8 NMOSFETS in series. With the extra CMOS inverter, the transistor count increases to 18. Compared to the other two NAND gates, this one has a medium area, longer delay and greater power dissipation. This makes its figure of merit the highest among the three NAND gates. See our Appendix page for a PSpice file, circuit diagram and output plot.

 

 

 

Figure 2 - MEDIUM TWO LEVEL AND: Two four-input NAND gate followed by one two-input NOR gate

 

 

In Figure 2, we have two four input CMOS NAND gates followed by a two input CMOS NOR gate. The combination of the gates provides a combined AND gate functionality. The two NAND gates each consists of 4 PMOSFETS in parallel and 4 NMOSFETS in series. The one NOR gate consists of two PMOSFETS in series and two NMOSFETS in parallel. In total, this gate contains 20 transistors. Compared to the other two AND gates, this one has a smaller area, medium delay and smaller power dissipation. This makes its figure of merit the lowest among the three AND gates. See our Appendix page for a PSpice file, circuit diagram and output plot.

 

 

 

Figure 3 - FOUR LEVEL AND: Four two-input NANDs followed by two two-input NORs then one two-input NAND terminated with an inverter

 

 

 

In Figure 3, we have four two input CMOS NAND gates followed by two two input CMOS NOR gates. After that, we have two input NAND gate followed by an inverter. The combination of the previously mentioned gates provides a combined AND gate functionality. The four two input NAND gates each consists of two PMOSFETS in parallel and two NMOSFETS in series. The two NOR gates consists of two PMOSFETS in series and two NMOSFETS in parallel. The two input NAND gate consists of two PMOSFETS in parallel and two NMOSFETS in series. In total, this gate contains 30 transistors. Compared to the other two AND gates, this gate has a greater area, smaller delay and larger power dissipation. This makes its figure of merit the second best among the three AND gates. See our Appendix page for a PSpice file, circuit diagram and output plot.

 

 

Figure 4 - CUSTOM BIG TWO LEVEL AND: An eight-input NAND gate followed by an inverter

 

 

Parameter(s) changed Tplh (ns) Tphl (ns) Tp (ns) Area (um^2) Power (mW) FOM Notes
All W/L changed to .25/.25 >15 >15 >15 1.125 0.0647818 ??? Hovers below Vm
 Inverter Pull-up changed to  .5/.25  >15 >15 >15 1.1875  0.12386356  ??? Same
 Inverter Pull-up changed to  1/.25 6.56353 10.45653 8.51003 1.3125 0.16041701 1.791764057 Cannot recover from Vout = 0 or 2.5
 Inverter Pull-up changed to 4/.25; Pull-down changed to .5/.25 2.47524 5.25558 3.86541 2.125 0.3459248 2.84142501 Final design
Table 2 - Design process for the custom big two-level AND gate

 

In Figure 4, we have the same eight input CMOS NAND gate as in Figure 1. After the group's moderate success at improving the circuit shown in Figure 2, Edward had a conversation with a colleage (Patrick Beck) that indicated that the big two-level AND gate had greater potential due in part to its small transistor count. From experience with resizing transistors in the medium two-level AND gate, we knew that reducing the transistor area reduced the power dissapation as well, decreasing two components of our FOM. From there, we hypothesized that since only the inverter's transistors drove a significant load, they would be the only ones requiring further resizing. Table 1 summarizes the design process of the big two-level AND gate. See our Appendix page for a PSpice file, circuit diagram and output plot.

 


1) Block diagrams of AND gates courtesy of D. Braun.

 

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